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Gate Current Modeling and Optimization of High-k Gate Stack MOSFET Structure in Nano Scale Regime
Ashwani RanaRelated information
1 Department of Electronics and Communication, National Institute of Technology, Hamirpur, Hamirpur (H.P)-177005, India
, Narottam ChandRelated information2 Department of Computer Science and Engineering, National Institute of Technology, Hamirpur, Hamirpur (H.P.)-177005, India
, Vinod KapoorRelated information1 Department of Electronics and Communication, National Institute of Technology, Hamirpur, Hamirpur (H.P)-177005, India